An Electrically Alterable Read Only Memory (EAROM) is used as programmable non-volatile semiconductor memory device. Such memory devices in the form of individual memory cells of metal nitride-oxide semiconductor (MNOS) construction, have source and drain regions and a memory gate region formed by an interface of insulating materials, for example, silicon dioxide and silicon nitride. EAROM devices can be laid down as part of an integrated circuit (IC) chip in predetermined patterns or arrays, with high density at a relatively low cost.
The IC also contains logic, addressing and decoding circuits for selecting groups of cells, with each group generally considered to constitute a word, or to select individual cells. EAROMs require low power and are relatively simple to erase and write into by applying appropriate voltages to the gate electrodes of the memory cells. They have found widespread use in a variety of applications, for example, radio and television tuners, program storage circuits, etc.
In EAROM devices of this type, each cell is isolated from the next so that any cell can be selected and read, written or erased without affecting another cell. Such isolation is often provided by using channel stops between adjacent groups of cells. A channel stop is an area on the substrate of the semiconductor device between adjacent cells with a high threshold voltage to prevent undesired communication between unrelated source-drain diffusion regions. This can be done by having a thick insulating material over a heavily doped substrate region between two unrelated source-drain diffusion regions. For example, in N-channel devices, the channel stops would be P.sup.+ type material, with a thick field insulation. However, even such techniques as channel stops do not fully solve the isolation problem in memory devices where the neighboring memory cells (bits) also have to be shielded from the write operations being performed on one of the neighboring bits.
In EAROM devices, channel shielding is defined as the ability to selectively write some of the desired memory cells from the erased state without affecting the other erased cells. In other words, it is the ability of write protecting an erased bit while the other neighboring bits are being written. Good channel shielding is both necessary and desirable for large, high density, memory structures. It is desirable to maintain good channel shielding throughout as many erase-write cycles as possible since this enhances the utility of the device.
In the channel shield mode, the source and drains (columns) of the unselected erased bit (bit which has to be channel shielded from the neighboring bits) are pre-charged to write voltage (about +25V for N-channel EAROMS). The gate (word line) is also raised to the write voltage and the substrate is at ground potential. Thus, the source, drain and gate are at the same potential, with source and drain junctions being reverse biased. The gate electrode current which otherwise would have been used to write this particular bit, is now substantially shunted by the reverse biased source and drain. Except due to some residual gate to substrate current, this particular bit would not be written. The smaller the amount of this residual gate current, the better is the channel shielding. As the erase-write operation is repeated, the effect of this residual current accumulates and the bit eventually loses its original erased state. Therefore, the time and the number of erase-write cycles effect the channel shielding. It is desirable to reduce the residual gate current in the channel shield mode and thus increase the number of erase-write cycles for which the channel shielding would be effective.